module copy #(
    parameter int unsigned WIDTH = 32
) (
    input  logic             clk,
    input  logic             rst_n,
    input  logic [WIDTH-1:0] in_data,
    input  logic             in_valid,
    output logic             in_ready,
    output logic [WIDTH-1:0] out0_data,
    output logic             out0_valid,
    input  logic             out0_ready,
    output logic [WIDTH-1:0] out1_data,
    output logic             out1_valid,
    input  logic             out1_ready
);
    assign in_ready   = out0_ready && out1_ready;
    assign out0_data  = in_data;
    assign out1_data  = in_data;
    assign out0_valid = in_valid;
    assign out1_valid = in_valid;
endmodule
